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8 Mbit Firmware Hub
A Microchip Technology Company
SST49LF008A
Data Sheet
Abort Mechanism
If FWH4 is driven low for one or more clock cycles during a FWH cycle, the cycle will be terminated
and the device will wait for the ABORT command. The host may drive the FWH[3:0] with ‘1111b’
(ABORT command) to return the device to Ready mode. If abort occurs during a Write operation, the
data may be incorrectly altered.
Response To Invalid Fields
During FWH operations, the FWH will not explicitly indicate that it has received invalid field sequences.
The response to specific invalid fields or sequences is as follows:
Address out of range:
The FWH address sequence is 7 fields long (28 bits), but only the last five address fields (20 bits) will
be decoded by SST49LF008A.
Address A 22 has the special function of directing reads and writes to the flash core (A 22 =1) or to the
register space (A 22 =0).
Invalid IMSIZE field:
If the FWH receives an invalid size field during a Read or Write operation, the device will reset and no
operation will be attempted. The SST49LF008A will not generate any kind of response in this situation.
Invalid-size fields for a Read/Write cycle are anything but 0000b.
Device Memory Hardware Write Protection
The Top Boot Lock (TBL#) and Write Protect (WP#) pins are provided for hardware write protection of
device memory in the SST49LF008A. The TBL# pin is used to write protect 16 boot sectors (64 KByte)
at the highest flash memory address range for the SST49LF008A. WP# pin write protects the remain-
ing sectors in the flash memory.
An active low signal at the TBL# pin prevents Program and Erase operations of the top boot sectors.
When TBL# pin is held high, write protection of the top boot sectors is then determined by the Boot
Block Locking register. The WP# pin serves the same function for the remaining sectors of the device
memory. The TBL# and WP# pins write protection functions operate independently of one another.
Both TBL# and WP# pins must be set to their required protection states prior to starting a Program or
Erase operation. A logic level change occurring at the TBL# or WP# pin during a Program or Erase
operation could cause unpredictable results. TBL# and WP# pins cannot be left unconnected.
TBL# is internally OR’ed with the top Boot Block Locking register. When TBL# is low, the top Boot
Block is hardware write protected regardless of the state of the Write-Lock bit for the Boot Block Lock-
ing register. Clearing the Write-Protect bit in the register when TBL# is low will have no functional
effect, even though the register may indicate that the block is no longer locked.
WP# is internally OR’ed with the Block Locking register. When WP# is low, the blocks are hardware
write protected regardless of the state of the Write-Lock bit for the corresponding Block Locking regis-
ters. Clearing the Write-Protect bit in any register when WP# is low will have no functional effect, even
though the register may indicate that the block is no longer locked.
?2011 Silicon Storage Technology, Inc.
12
DS25085A
10/11
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